MCF51AC128AVPUE Freescale Semiconductor, MCF51AC128AVPUE Datasheet - Page 31
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MCF51AC128AVPUE
Manufacturer Part Number
MCF51AC128AVPUE
Description
MCU 32BIT 128K FLASH CAN 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51ACr
Datasheet
1.MCF51AC128CCFUE.pdf
(50 pages)
Specifications of MCF51AC128AVPUE
Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
LVD, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 20x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
MCF51AC
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
50.33 MHz
Number Of Programmable I/os
54
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 20 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF51AC128AVPUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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2.11
This section describes ac timing characteristics for each peripheral system.
Freescale Semiconductor
Num C
18
19
20
21
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
The resulting bus clock frequency must not exceed the maximum specified bus clock frequency of the device.
This specification applies when the FLL reference source or reference divider is changed, trim value changed or changing from
FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
This specification applies when the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
a given interval.
625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and
the sample point of a bit using 8 time quanta per bit.
Below D
lock, then the MCG may stay in lock.
Below D
Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 105 C Ambient)
D Lock exit frequency tolerance
D Lock time — FLL
D Lock time — PLL
D
Loss of external clock minimum frequency —
RANGE = 0
lock
unl
AC Characteristics
minimum, the MCG will not exit lock if already in lock. Above D
minimum, the MCG enters lock. Above D
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.6
Rating
DD
and V
8
SS
and variation in crystal oscillator frequency increase the C
lock
maximum, the MCG will not enter lock. But if the MCG is already in
o
Symbol
t
f
t
pll_lock
loc_low
fll_lock
D
unl
unl
maximum, the MCG is guaranteed to exit lock.
(3/5) f
4.47
Min
—
—
int
Typical
—
—
—
—
Electrical Characteristics
1
1075(1/
1075(1/
t
t
pll_acquire+
fll_acquire+
5.97
Jitter
Max
—
f
pll_ref)
f
int_t)
percentage for
BUS
.
Unit
kHz
%
s
s
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