R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 125

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
13.2
Table 13.3
NOTES:
Count source
Count operation
Period
Count start conditions
Reset condition of watchdog
timer
Count stop condition
Operation at time of
underflow
Registers, bits
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer. Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode
Enabled).
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
0FFFFh with a flash programmer.
CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address
0FFFFh with a flash programmer.
Count Source Protection Mode Enabled
Dec 08, 2006
Item
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Page 107 of 315
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
Example: Period is approximately 32.8 ms when the low-speed on-chip
The WDTON bit
the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
• When the WDTON bit is set to 0 (watchdog timer starts automatically
• Reset
• Write 00h to the WDTR register before writing FFh.
• Underflow
None (The count does not stop in wait mode after the count starts. The
MCU does not enter stop mode.)
Watchdog timer reset (Refer to 6.5 Watchdog Timer Reset.)
• When setting the CSPPRO bit in the CSPR register to 1 (count source
• The following conditions apply in count source protection mode
Low-speed on-chip oscillator clock
reset).
after reset).
The watchdog timer and prescaler start counting automatically after a
reset.
protection mode is enabled)
when the WDTS register is written to.
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip oscillator
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is reset
The watchdog timer and prescaler stop after a reset and the count starts
- Writing to the CM14 bit in the CM1 register is disabled. (It remains
- Writing to the CM10 bit in the CM1 register is disabled. (It remains
unchanged even if it is set to 1. The MCU does not enter stop mode.)
unchanged even if it is set to 1. The low-speed on-chip oscillator does
not stop.)
on)
when watchdog timer underflows)
oscillator clock frequency is 125 kHz
(1)
in the OFS register (0FFFFh) selects the operation of
(2)
Specification
, the following are set automatically
13. Watchdog Timer