MC908AP8CFAE Freescale Semiconductor, MC908AP8CFAE Datasheet - Page 199
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MC908AP8CFAE
Manufacturer Part Number
MC908AP8CFAE
Description
IC MCU 8K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908AP8CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP8CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908AP8CFAE
Manufacturer:
FREESCALE
Quantity:
20 000
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M — Mode (Character Length) Bit
WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
PEN — Parity Enable Bit
PTY — Parity Bit
Freescale Semiconductor
This read/write bit determines whether SCI characters are eight or nine bits long. (See
The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the RxD pin. Reset clears the
WAKE bit.
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then
a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning
the count after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
This read/write bit enables the SCI parity function. (See
inserts a parity bit in the most significant bit position. (See
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See
1 = 9-bit SCI characters
0 = 8-bit SCI characters
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
Table
12-6.) Reset clears the PTY bit.
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
M
0
1
0
0
1
1
Control Bits
PEN:PTY
0X
0X
10
11
10
11
Table 12-6. Character Format Selection
MC68HC908AP Family Data Sheet, Rev. 4
Start
Bits
1
1
1
1
1
1
Data
Bits
NOTE
8
9
7
7
8
8
Character Format
Table
Parity
None
None
Even
Even
Odd
Odd
Figure
12-6.) When enabled, the parity function
12-6.) Reset clears the PEN bit.
Stop
Bits
1
1
1
1
1
1
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Table
I/O Registers
12-6.)
199
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