MC9S08DV96MLF Freescale Semiconductor, MC9S08DV96MLF Datasheet - Page 182
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MC9S08DV96MLF
Manufacturer Part Number
MC9S08DV96MLF
Description
MCU 8BIT 96K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV96MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV96MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock.
The external reference clock which is enabled can be an external crystal/resonator or it can be another
external clock source.
The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available
for BDC communications. If the BDM becomes active the mode will switch to one of the bypassed
external modes as determined by the state of the PLLS bit.
In this mode, the DRST bit reads 0 regardless of whether the DRS bit is set to 1 or 0.
8.4.1.9
Stop mode is entered whenever the MCU enters a STOP state. In this mode, the FLL and PLL are disabled
and all MCG clock signals are static except in the following cases:
MCGIRCLK will be active in stop mode when all the following conditions occur:
MCGERCLK will be active in stop mode when all the following conditions occur:
8.4.2
The IREFS bit can be changed at anytime, but the actual switch to the newly selected clock is shown by
the IREFST bit. When switching between engaged internal and engaged external modes, the FLL or PLL
will begin locking again after the switch is completed.
For the special case of entering stop mode immediately after switching to FBE mode, if the external clock
and the internal clock are disabled in stop mode, (EREFSTEN = 0 and IREFSTEN = 0), it is necessary to
allow 100us after the IREFST bit is cleared to allow the internal reference to shutdown. For most cases the
delay due to instruction execution times will be sufficient.
The CLKS bits can also be changed at anytime, but the actual switch to the newly selected clock is shown
by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected.
The DRS bits can be changed at anytime except when LP bit is 1. If the DRS bits are changed while in
FLL engaged internal (FEI) or FLL engaged external (FEE), the bus clock remains at the previous DCO
range until the new DCO starts. When the new DCO starts the bus clock switches to it. After switching to
the new DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time
is over, the FLL is locked. The completion of the switch is shown by the DRST bits.
For details see
182
•
•
•
•
•
BDM mode is not active
IRCLKEN = 1
IREFSTEN = 1
ERCLKEN = 1
EREFSTEN = 1
Mode Switching
Stop
Figure
8-9.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
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