MC9S08DV60AMLF Freescale Semiconductor, MC9S08DV60AMLF Datasheet - Page 14

• Manufacturer Part Number: MC9S08DV60AMLF
• Description: IC MCU 60K FLASH 3K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV60AMLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Section Number
11.4 Functional Description ...................................................................................................................207
11.5 Resets .............................................................................................................................................212
11.6 Interrupts ........................................................................................................................................212
11.7 Initialization/Application Information ...........................................................................................214
12.1 Introduction ....................................................................................................................................217
12.2 External Signal Description ...........................................................................................................220
12.3 Register Definition .........................................................................................................................221
14
11.3.1 IIC Address Register (IICA) ...........................................................................................201
11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................201
11.3.3 IIC Control Register (IICC1) ..........................................................................................204
11.3.4 IIC Status Register (IICS) ...............................................................................................205
11.3.5 IIC Data I/O Register (IICD) ..........................................................................................206
11.3.6 IIC Control Register 2 (IICC2) .......................................................................................206
11.4.1 IIC Protocol .....................................................................................................................207
11.4.2 10-bit Address .................................................................................................................211
11.4.3 General Call Address ......................................................................................................212
11.6.1 Byte Transfer Interrupt ....................................................................................................212
11.6.2 Address Detect Interrupt .................................................................................................212
11.6.3 Arbitration Lost Interrupt ................................................................................................212
12.1.1 Features ...........................................................................................................................219
12.1.2 Modes of Operation ........................................................................................................219
12.1.3 Block Diagram ................................................................................................................220
12.2.1 RXCAN — CAN Receiver Input Pin .............................................................................220
12.2.2 TXCAN — CAN Transmitter Output Pin .....................................................................220
12.2.3 CAN System ...................................................................................................................220
12.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................221
12.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................224
12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ...............................................................225
12.3.4 MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................226
12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................229
12.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................................230
12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) ........................................231
12.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) ...........................232
12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) .................233
12.3.10MSCAN Transmit Buffer Selection Register (CANTBSEL) .........................................233
12.3.11MSCAN Identifier Acceptance Control Register (CANIDAC) ......................................234
12.3.12MSCAN Miscellaneous Register (CANMISC) ..............................................................235
12.3.13MSCAN Receive Error Counter (CANRXERR) ............................................................236
12.3.14MSCAN Transmit Error Counter (CANTXERR) ..........................................................237
Freescale Controller Area Network (S08MSCANV1)
MC9S08DV60 Series Data Sheet, Rev 3
Chapter 12
Subject to Change
Title
Freescale Semiconductor
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