MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 393
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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All TPM channels are programmable independently as input capture, output compare, or buffered
edge-aligned PWM channels.
B.1
When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled.
After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive
pullups disabled.
B.1.1
When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and
consequently the 16-bit counter for TPMx are driven by an external clock source, TPMxCLK, connected
to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This
synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half
the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to
be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL)
or frequency-locked loop (FLL) frequency jitter effects.
On some devices the external clock input is shared with one of the TPM channels. When a TPM channel
is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still
be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the
external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not
trying to use the same pin.
B.1.2
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled
by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction
registers do not affect the related pin(s). See the
about shared pin functions.
B.2
The TPM includes:
Each timer channel has:
Refer to the direct-page register summary in the
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale Semiconductor
•
•
•
•
•
An 8-bit status and control register (TPMxSC)
A 16-bit counter (TPMxCNTH:TPMxCNTL)
A 16-bit modulo register (TPMxMODH:TPMxMODL)
An 8-bit status and control register (TPMxCnSC)
A 16-bit channel value register (TPMxCnVH:TPMxCnVL)
External Signal Description
Register Definition
External TPM Clock Sources
TPMxCHn — TPMx Channel n I/O Pins
MC9S08DZ60 Series Data Sheet, Rev. 4
Memory
Pins and Connections
chapter of this data sheet for the absolute address
Appendix B Timer Pulse-Width Modulator (TPMV2)
chapter for additional information
393
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