C8051F353-GMR Silicon Laboratories Inc, C8051F353-GMR Datasheet - Page 7
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C8051F353-GMR
Manufacturer Part Number
C8051F353-GMR
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F353-GMR
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
For Use With
336-1083 - DEV KIT FOR F350/351/352/353
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
List of Figures
1. System Overview
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
5. 24 or 16-Bit Analog to Digital Converter (ADC0)
6. 8-Bit Current Mode DACS (IDA0 and IDA1)
7. Voltage Reference
8. Temperature Sensor
9. Comparator0
10. CIP-51 Microcontroller
Figure 1.1. C8051F350 Block Diagram .................................................................... 19
Figure 1.2. C8051F351 Block Diagram .................................................................... 19
Figure 1.3. C8051F352 Block Diagram .................................................................... 20
Figure 1.4. C8051F353 Block Diagram .................................................................... 20
Figure 1.5. Development/In-System Debug Diagram............................................... 22
Figure 1.6. Memory Map .......................................................................................... 23
Figure 1.7. ADC0 Block Diagram ............................................................................. 24
Figure 1.8. IDAC Block Diagram .............................................................................. 25
Figure 1.9. Comparator0 Block Diagram.................................................................. 26
Figure 1.10. Port I/O Functional Block Diagram ....................................................... 27
Figure 1.11. PCA Block Diagram.............................................................................. 28
Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 34
Figure 4.2. QFN-28 Pinout Diagram (Top View) ...................................................... 35
Figure 4.3. LQFP-32 Package Diagram ................................................................... 36
Figure 4.4. QFN-28 Package Drawing ..................................................................... 37
Figure 4.5. Typical QFN-28 Landing Diagram.......................................................... 38
Figure 4.6. Typical QFN-28 Solder Paste Diagram.................................................. 39
Figure 5.1. ADC0 Block Diagram ............................................................................. 41
Figure 5.2. ADC0 Buffer Control .............................................................................. 43
Figure 5.3. ADC0 Offset Calibration Register Coding .............................................. 45
Figure 5.4. ADC0 Gain Calibration Register Coding ................................................ 45
Figure 5.5. ADC0 Multiplexer Connections .............................................................. 59
Figure 6.1. IDAC Functional Block Diagram............................................................. 67
Figure 6.2. IDAC Data Word Mapping...................................................................... 68
Figure 6.3. IDAC Pin Connections ........................................................................... 71
Figure 7.1. Reference Circuitry Block Diagram ........................................................ 73
Figure 8.1. Temperature Sensor Block Diagram...................................................... 77
Figure 8.2. Single Channel Transfer Function.......................................................... 78
Figure 8.3. Differential Transfer Function................................................................. 78
Figure 9.1. Comparator0 Functional Block Diagram ................................................ 79
Figure 9.2. Comparator Hysteresis Plot ................................................................... 80
Figure 9.3. Comparator Pin Connections ................................................................. 83
Figure 10.1. CIP-51 Block Diagram.......................................................................... 87
Rev. 1.1
C8051F350/1/2/3
7