MC9S12P96MFT Freescale Semiconductor, MC9S12P96MFT Datasheet - Page 133
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MC9S12P96MFT
Manufacturer Part Number
MC9S12P96MFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5.1.2.3
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware
commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case
the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also
the CPU can not enter a low power mode (stop or wait) during BDM active mode.
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
5.1.3
A block diagram of the BDM is shown in
5.2
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
Freescale Semiconductor
System
Host
External Signal Description
Block Diagram
Low-Power Modes
Register Block
BKGD
BDMSTS
Register
BDMACT
ENBDM
UNSEC
TRACE
SDV
Interface
The communication rate of this pin is based on the settings for the VCO clock
Serial
S12P-Family Reference Manual, Rev. 1.13
Control
Data
Figure 5-1. BDM Block Diagram
Figure
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
5-1.
Execution
and
Background Debug Module (S12SBDMV1)
Bus Interface
Control Logic
and
Address
Data
Control
Clocks
133
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