MC908QL4MDTER Freescale Semiconductor, MC908QL4MDTER Datasheet - Page 185

• Manufacturer Part Number: MC908QL4MDTER
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QL4MDTER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHxMAX — Channel x Maximum Duty Cycle Bit
15.8.5 TIM Channel Registers
These read/write registers contain the captured counter value of the input capture function or the output
compare value of the output compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Freescale Semiconductor
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Reset:
Reset:
Read:
Write:
Read:
Write:
TCHx
CHxMAX
OVERFLOW
Bit 15
Bit 7
Bit 7
Bit 7
Figure 15-12. TIM Channel x Register High (TCHxH)
Figure 15-13. TIM Channel Register Low (TCHxL)
COMPARE
PERIOD
Figure 15-11
OUTPUT
Bit 14
Bit 6
6
6
OVERFLOW
Figure 15-11. CHxMAX Latency
MC68HC908QL4 Data Sheet, Rev. 8
Bit 13
Bit 5
5
5
shows, the CHxMAX bit takes effect in the cycle after it is set
COMPARE
OUTPUT
Indeterminate after reset
Indeterminate after reset
Bit 12
Bit 4
OVERFLOW
4
4
Bit 11
COMPARE
Bit 3
OUTPUT
3
3
OVERFLOW
Bit 10
Bit 2
2
2
COMPARE
OUTPUT
Bit 9
Bit 1
1
1
OVERFLOW
Bit 0
Bit 8
Bit 0
Bit 0
Registers
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