MC908JL16CDWE Freescale Semiconductor, MC908JL16CDWE Datasheet - Page 136

• Manufacturer Part Number: MC908JL16CDWE
• Description: IC MCU 16K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ADC)
ADLSMP — Long Sample Time Configuration
ACLKEN — Asynchronous Clock Source Enable
136
This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize
conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption in continuous conversion mode if high conversion rates are not required.
This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK,
and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and
2 MHz if the ADLPC bit is clear, and between 0.5 MHz and 1 MHz if the ADLPC bit is set. As long as
the internal clock ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency
(f
operation is guaranteed.
ADCK
1 = Long sample time (23.5 cycles)
0 = Short sample time (3.5 cycles)
1 = The asynchronous clock is selected as the input clock source (the clock generator is only
0 = The ADICLK bit specifies the input clock source and conversions will not continue in stop mode
) between the minimum and maximum required clock frequencies (considering ALPC), correct
enabled during the conversion)
MC68HC908JL16 Data Sheet, Rev. 1.1
Freescale Semiconductor