C8051F313-GMR Silicon Laboratories Inc, C8051F313-GMR Datasheet - Page 107

• Manufacturer Part Number: C8051F313-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F313-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

any other reset source. For example, if the V
V
Important Note: The V
V
dure for configuring the V
See Figure 9.2 for V
See Table 9.1 for complete electrical characteristics of the V
9.3.
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.1 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
DD
DD
Bit7:
Bit6:
Bits5–0: Reserved. Read = Variable. Write = don’t care.
VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
monitor will still be enabled after the reset.
monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-
R/W
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
External Reset
VDMEN: V
This bit is turns the V
resets until it is also selected as a reset source in register RSTSRC (Figure 9.2). The V
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 9.1 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
DD
DD
DD
DD
DD
DD
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
monitor as a reset source before it has stabilized may generate a system reset.
STAT: V
Bit6
R
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
DD
SFR Definition 9.1. VDM0CN: V
DD
DD
monitor timing; note that the reset delay is not incurred after a V
DD
DD
Monitor Enable.
monitor must be enabled before it is selected as a reset source. Selecting the
Status.
monitor as a reset source is shown below:
DD
Bit5
DD
R
DD
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor to stabilize (see Table 9.1 for the V
DD
DD
monitor circuit on/off. The V
monitor threshold.
DD
Bit4
R
monitor threshold.
DD
DD
monitor is enabled and a software reset is performed, the
Monitor turn-on time.
Rev. 1.7
Bit3
R
C8051F310/1/2/3/4/5/6/7
DD
DD
Bit2
monitor.
R
DD
DD
Monitor Control
Monitor output).
Monitor cannot generate system
Bit1
R
DD
Monitor turn-on time).
SFR Address:
Bit0
R
DD
monitor reset.
0xFF
Reset Value
Variable
DD
107