MCHC908JK1ECPE Freescale Semiconductor, MCHC908JK1ECPE Datasheet - Page 45
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MCHC908JK1ECPE
Manufacturer Part Number
MCHC908JK1ECPE
Description
IC MCU 1.5K FLASH XTAL 20-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MCHC908JK1ECPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
14
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
HC08JK
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908JK1ECPE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Freescale Semiconductor
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA
PSHH
PSHX
Source
Form
Jump to Subroutine
Load A from M
Load H:X from M
Load X from M
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Inclusive OR A and M
Push A onto Stack
Push H onto Stack
Push X onto Stack
Jump
Operation
Table 4-1. Instruction Set Summary (Sheet 4 of 6)
MC68HC908JL3E Family Data Sheet, Rev. 4
PC ← (PC) + n (n = 1, 2, or 3)
H:X ← (H:X) + 1 (IX+D, DIX+)
PC ← Unconditional Address
Push (PCH); SP ← (SP) – 1
Push (PCL); SP ← (SP) – 1
0
C
(M)
Push (H); SP ← (SP) – 1
Push (A); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
PC ← Jump Address
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
A ← (A[3:0]:A[7:4])
Destination
b7
H:X ← (M:M + 1)
b7
X:A ← (X) × (A)
Description
A ← (A) | (M)
A ← (M)
X ← (M)
None
← (M)
b0
b0
Source
C
0
V H I N Z C
– – – – – –
– – – – – –
0 – –
0 – –
0 – –
0 – –
– 0 – – – 0 INH
– – – – – – INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– –
– – 0
– –
on CCR
Effect
Instruction Set Summary
–
–
–
–
–
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
9EDE
9EE6
9ED6
9EEE
9EEA
9EDA
9E68
9E64
9E60
CC
DC
CD
DD
BC
EC
FC
BD
ED
FD
C6
D6
AE
BE
CE
DE
EE
FE
9D
AA
BA
CA
DA
EA
A6
B6
E6
F6
45
55
38
48
58
68
78
34
44
54
64
74
4E
5E
6E
7E
42
30
40
50
60
70
62
FA
87
8B
89
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii jj
dd
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
45
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
3
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
5
4
4
4
5
4
1
1
4
3
5
1
3
2
3
4
4
3
2
4
5
2
2
2