C8051F331-GMR Silicon Laboratories Inc, C8051F331-GMR Datasheet - Page 192

• Manufacturer Part Number: C8051F331-GMR
• Description: IC 8051 MCU 8K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• For Use With: 336-1451 - ADAPTER PROGRAM TOOLSTICK F330336-1264 - DEV KIT FOR C8051F330/F331
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

C8051F330/1/2/3/4/5
19.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
196
Port I/O
hardware.
Crossbar
Figure 19.4. PCA Capture Mode Diagram
CEXn
W
M
P
1
6
n
x
PCA0CPMn
E
C
O
M
n
0
C
A
P
P
n
Rev. 1.7
C
N
A
P
n
0
1
M
A
T
n
x 0 0 x
O
G
T
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
PCA
Timebase
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H