MC908QB4CDWE Freescale Semiconductor, MC908QB4CDWE Datasheet - Page 118

• Manufacturer Part Number: MC908QB4CDWE
• Description: IC MCU 8BIT 4K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QB4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Controller Family/series: HC08
• No. Of I/o's: 14
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Serial Communications Interface (ESCI) Module
Slow Data Tolerance
Figure 13-7
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles
+ 10 RT cycles = 154 RT cycles.
With the misaligned character shown in
the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is:
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles
+ 10 RT cycles = 170 RT cycles.
With the misaligned character shown in
the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
Fast Data Tolerance
Figure 13-8
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
118
shows how much a slow received character can be misaligned without causing a noise error
shows how much a fast received character can be misaligned without causing a noise error
RECEIVER
RT CLOCK
RECEIVER
RT CLOCK
MC68HC908QB8 Data Sheet, Rev. 3
MSB
Figure
Figure
Figure 13-7. Slow Data
154 147
------------------------- -
170 163
------------------------- -
Figure 13-8. Fast Data
154
170
STOP
–
–
13-7, the receiver counts 154 RT cycles at the point when
13-7, the receiver counts 170 RT cycles at the point when
×
×
100
100
DATA SAMPLES
SAMPLES
=
=
DATA
4.54%
4.12%
IDLE OR NEXT CHARACTER
STOP
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