MC9S08AC60CFDE Freescale Semiconductor, MC9S08AC60CFDE Datasheet - Page 81

IC MCU 8BIT 60K FLASH 48-QFN

MC9S08AC60CFDE

Manufacturer Part Number
MC9S08AC60CFDE
Description
IC MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08AC60CFDE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
3
Rohs Compliant
Yes
Height
1 mm
Length
7 mm
Supply Voltage (max)
5.5 V, 5.5 V
Supply Voltage (min)
2.7 V, 2.7 V
Width
7 mm
For Use With
DEMO9S08AC60E - BOARD DEMO FOR MC9S08A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
1
5.9.10
This high page register contains bits to configure MCU specific features on the MC9S08AC60 Series
devices.
Freescale Semiconductor
TPMCCFG
This bit can be written only one time after reset. Additional writes are ignored.
COPCLKS
Reset:
Field
7
3
W
R
COPCLKS
System Options Register 2 (SOPT2)
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
TPM Clock Configuration — Configures the timer/pulse-width modulator clock signal.
0 TPMCLK is available to TPM1, TPM2, and TPM3 via the IRQ pin; TPMCLK1 and TPMCLK2 are not available.
1 TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively.
1
7
1
= Unimplemented or Reserved
0
0
6
Figure 5-12. System Options Register 2 (SOPT2)
Table 5-14. SOPT2 Register Field Descriptions
MC9S08AC60 Series Data Sheet, Rev. 2
0
0
5
0
0
4
Description
TPMCCFG
Chapter 5 Resets, Interrupts, and System Configuration
3
1
0
0
2
0
0
1
0
0
0
81

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