C8051F523A-IM Silicon Laboratories Inc, C8051F523A-IM Datasheet - Page 32

• Manufacturer Part Number: C8051F523A-IM
• Description: IC 8051 MCU 4K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F523A-IM

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1491-5

C8051F52x/F52xA/F53x/F53xA
Table 2.7. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
32
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Impedance
V
V
Missing Clock Detector Timeout
Reset Time Delay
Minimum RST Low Time to Generate a
System Reset
V
V
Note: Refer to Section “20. Device Specific Behavior” on page 209.
DD
DD
DD
DD
Monitor Threshold (V
Monitor Threshold (V
Monitor Turn-on Time
Monitor Supply Current
Parameter
*
RST-LOW
RST-HIGH
)
)
I
2.1 V
V
V
V
V
C8051F52x/53x
C8051F52xA/53xA
C8051F52x/53x
C8051F52xA/53xA
Time from last system
clock rising edge to reset
initiation
Delay between release
of any reset source and
code execution at loca-
tion 0x0000
V
OL
REGIN
REGIN
REGIN
REGIN
DD
= 8.5 mA, V
= 2.1 V
Conditions
= 1.8 V
= 2.7 V
= 3.3 V
= 5 V
Rev. 1.3
DD
=
V
0.7 x
2.25
REGIN
Min
100
1.8
1.7
2.1
10
—
—
—
—
—
—
—
—
—
1.75
Typ
330
160
130
350
1.9
2.2
2.3
—
—
—
80
—
—
83
2
V
0.3 x
Max
REGIN
650
350
0.8
2.0
1.8
2.3
2.4
—
—
—
—
—
—
—
6
Units
k
k
k
k
µA
µs
µs
µs
µs
V
V
V
V
V
V
V