C8051F334-GMR Silicon Laboratories Inc, C8051F334-GMR Datasheet - Page 208
C8051F334-GMR
Manufacturer Part Number
C8051F334-GMR
Description
IC 8051 MCU 2K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F334-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
For Use With
336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F334-GMR
Manufacturer:
ZILLTEK
Quantity:
3 340
Part Number:
C8051F334-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051F330/1/2/3/4/5
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Revision 1.3 to Revision 1.4
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Revision 1.4 to Revision 1.5
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Revision 1.5 to Revision 1.6
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Revision 1.6 to Revision 1.7
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212
OCUMENT
Removed references to C8051F330D throughout the data sheet because the 'F330D device is func-
tionally identical to the C8051F330 device (these two part numbers differ by package type only).
Updated titles of Chapters 5, 6, and 7 to show supported devices.
Updated Table 1.1, “Product Selection Guide,” on page 18.
- Added ordering part number information for lead-free parts.
Added Table 3.2, “Index to Electrical Characteristics Tables,” on page 34
Added Table 11.2, “Flash Security Summary,” on page 106 for clarity, replacing the Flash security sum-
maries text.
Updated Table 3.1 - Added supply current data from characterization.
Updated Table 5.1 - Added MIN/MAX numbers for ADC Offset and Full Scale Error.
Fixed SFR Definition 8.2 - Typo in bit descriptions - “2-0” changed to “3-0”.
Fixed SFR Definition 9.4 - Text at bottom of figure was cut off.
Added
Fixed
changed to “upper 7 bits”.
Fixed text in
or 3072 system clock cycles”.
Changed Table 19.4, Note 2 to refer to SYSCLK reset frequency = Internal Oscillator / 8.
Fixed Equation 19.6, “Watchdog Timer Offset in PCA Clocks,” - Typo in equation - “PCA0CPL4”
changed to “PCA0CPL2”.
Updated package drawings.
Removed PDIP package information.
Section “12. External RAM” on page 111
Section “11.4. Flash Write and Erase Guidelines” on page 107
Section “19.3.2. Watchdog Timer Usage” on page 203
C
HANGE
L
IST
Rev. 1.7
, paragraph 2 - Typo in description - “upper 6-bits”
to read “256 PCA clock cycles,
.
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