MC9S08SH4CTG Freescale Semiconductor, MC9S08SH4CTG Datasheet - Page 158
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MC9S08SH4CTG
Manufacturer Part Number
MC9S08SH4CTG
Description
IC MCU 8BIT 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH4CTJ.pdf
(338 pages)
Specifications of MC9S08SH4CTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Bit Size
10 bit
A/d Channels Available
12
Height
1.05 mm
Length
5 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4.4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08SH4CTG
Manufacturer:
FREESCAL
Quantity:
96
Company:
Part Number:
MC9S08SH4CTG
Manufacturer:
Freescale
Quantity:
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Chapter 10 Internal Clock Source (S08ICSV2)
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 1024 times the reference frequency,
as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal
reference clock is enabled.
10.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock.The FLL loop will lock the frequency to 1024 times the reference frequency,
as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external
reference clock is enabled.
10.4.1.3
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 1024
times the reference frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC
communications, and the internal reference clock is enabled.
10.4.1.4
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
158
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CLKS bits are written to 00
IREFS bit is written to 1
RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
CLKS bits are written to 00
IREFS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is active or LP bit is written to 0
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is not active and LP bit is written to 1
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
FLL Bypassed Internal Low Power (FBILP)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
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