S9S08SG4E2MTG Freescale Semiconductor, S9S08SG4E2MTG Datasheet - Page 78
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S9S08SG4E2MTG
Manufacturer Part Number
S9S08SG4E2MTG
Description
MCU 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2MTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6 Parallel Input/Output Control
6.6.1
Port A is controlled by the registers listed below.
6.6.1.1
6.6.1.2
77
PTADD[3:0]
PTAD[3:0]
Reserved
Reserved
Reset:
Reset:
Field
Field
5:4
3:0
5:4
3:0
W
W
R
R
Port A Registers
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Port A Data Register (PTAD)
0
0
Port A Data Direction Register (PTADD)
0
0
7
7
0
0
0
0
6
6
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-3. PTADD Register Field Descriptions
Table 6-2. PTAD Register Field Descriptions
Figure 6-3. Port A Data Register (PTAD)
MC9S08SG8 MCU Series Data Sheet, Rev. 6
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
PTADD3
PTAD3
3
0
3
0
PTADD2
PTAD2
0
0
2
2
PTADD1
Freescale Semiconductor
PTAD1
0
0
1
1
PTADD0
PTAD0
0
0
0
0
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