S9S08SG4E2CSC Freescale Semiconductor, S9S08SG4E2CSC Datasheet - Page 101
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S9S08SG4E2CSC
Manufacturer Part Number
S9S08SG4E2CSC
Description
MCU 4K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2CSC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Freescale Semiconductor
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Source
Form
Increment
Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – $0001
Push (PCH); SP ← (SP) – $0001
PC ← Unconditional Address
Load Accumulator from Memory
A ← (M)
Load Index Register (H:X)
H:X ← (M:M + $0001)
Load X (Index Register Low) from Memory
X ← (M)
Logical Shift Left
(Same as ASL)
Logical Shift Right
0
C
b7
b7
M ← (M) + $01
A ← (A) + $01
X ← (X) + $01
M ← (M) + $01
M ← (M) + $01
M ← (M) + $01
Table 7-2. Instruction Set Summary (Sheet 5 of 9)
Operation
b0
b0
MC9S08SG8 MCU Series Data Sheet, Rev. 6
C
0
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX
IX2
IX1
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
Object Code
9E 6C
9E D6
9E E6
9E AE
9E BE
9E CE
9E FE
9E DE
9E EE
9E 68
9E 64
3C
4C
5C
6C
7C
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
45
55
32
AE
BE
CE
DE
EE
FE
38
48
58
68
78
34
44
54
64
74
dd
ff
ff
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
jj kk
dd
hh ll
ee ff
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
Chapter 7 Central Processor Unit (S08CPUV2)
5
1
1
5
4
6
3
4
4
3
3
5
6
6
5
5
2
3
4
4
3
3
5
4
3
4
5
5
6
5
5
2
3
4
4
3
3
5
4
5
1
1
5
4
6
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
ppp
pppp
pppp
ppp
ppp
ssppp
pssppp
pssppp
ssppp
ssppp
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
ppp
rrpp
prrpp
prrfp
pprrpp
prrpp
prrpp
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
rfwpp
p
p
rfwpp
rfwp
prfwpp
rfwpp
p
p
rfwpp
rfwp
prfwpp
Cyc-by-Cyc
Details
V 1 1 H I N Z C
↕ 1 1 – – ↕ ↕ –
– 1 1 – – – – –
– 1 1 – – – – –
0 1 1 – – ↕ ↕ –
0 1 1 – – ↕ ↕ –
0 1 1 – – ↕ ↕ –
↕ 1 1 – – ↕ ↕ ↕
↕ 1 1 – – 0 ↕ ↕
on CCR
Affect
101
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