MC9S08SH4MSC Freescale Semiconductor, MC9S08SH4MSC Datasheet - Page 282
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MC9S08SH4MSC
Manufacturer Part Number
MC9S08SH4MSC
Description
IC MCU 8BIT 4K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH4CTJ.pdf
(338 pages)
Specifications of MC9S08SH4MSC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Active BDM:
Chapter 17 Development Support
17.4.1.1
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
Reset in
282
Normal
Reset
BDMACT
BKPTEN
ENBDM
CLKSW
Field
FTS
W
7
6
5
4
3
R
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
clock source.
0 Alternate BDC clock source
1 MCU bus clock
0
1
7
BDC Status and Control Register (BDCSCR)
instruction
opcode)
= Unimplemented or Reserved
BDMACT
Figure 17-5. BDC Status and Control Register (BDCSCR)
0
1
6
Table 17-2. BDCSCR Register Field Descriptions
MC9S08SH8 MCU Series Data Sheet, Rev. 3
BKPTEN
0
0
5
FTS
0
0
4
Description
CLKSW
0
1
3
WS
0
0
2
Freescale Semiconductor
WSF
1
0
0
DVF
0
0
0
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