C8051T604-GM Silicon Laboratories Inc, C8051T604-GM Datasheet - Page 126
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C8051T604-GM
Manufacturer Part Number
C8051T604-GM
Description
IC 8051 MCU 2K-EEPROM 11-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T604-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
2KB (2K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1658-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T604-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
C8051T600/1/2/3/4/5/6
SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration
SFR Address = 0xC1
126
Name
Reset
1:0 SMBCS[1:0] SMBus Clock Source Selection.
Bit
Type
7
6
5
4
3
2
Bit
EXTHOLD
SMBTOE
SMBFTE
ENSMB
Name
BUSY
ENSMB
INH
R/W
7
0
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 23.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 23.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
R/W
INH
6
0
BUSY
R
5
0
EXTHOLD SMBTOE
R/W
Rev. 1.2
4
0
Function
R/W
3
0
SMBFTE
R/W
2
0
1
0
SMBCS[1:0]
R/W
0
0