MC9S08QG8CDNE Freescale Semiconductor, MC9S08QG8CDNE Datasheet - Page 220
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MC9S08QG8CDNE
Manufacturer Part Number
MC9S08QG8CDNE
Description
IC MCU 8K FLASH 8MHZ 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8CDNE
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Serial Peripheral Interface (S08SPIV3)
Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These
changes should be performed as separate operations or unexpected behavior may occur.
15.4.2
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
218
Reset
LSBFE
MSTR
CPHA
SSOE
CPOL
Field
4
3
2
1
0
W
R
SPI Control Register 2 (SPIC2)
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
MODFEN
0
0
7
0
0
1
1
= Unimplemented or Reserved
0
0
6
Section 15.5.1, “SPI Clock
SSOE
Table 15-1. SPIC1 Field Descriptions (continued)
0
1
0
1
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 15-6. SPI Control Register 2 (SPIC2)
Section 15.5.1, “SPI Clock
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
0
0
5
Table 15-2. SS Pin Function
MODFEN
Master Mode
NOTE
Formats”
0
4
Description
Formats”
for more details.
BIDIROE
3
0
for more details.
Slave select input
Slave select input
Slave select input
Slave select input
0
0
2
Slave Mode
SPISWAI
Freescale Semiconductor
0
1
Table
SPC0
0
0
15-2.
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