STR750FV1T6 STMicroelectronics, STR750FV1T6 Datasheet - Page 48

• Manufacturer Part Number: STR750FV1T6
• Description: MCU 32BIT 128KB FLASH 100-LQFP
• Manufacturer: STMicroelectronics
• Series: STR7r

Specifications of STR750FV1T6

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, SPI, SSI, SSP, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: STR750x
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SPI, SSI, SSP, USB
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, KSDK-STR750-PLUS, MCBSTR750, MCBSTR750U, MCBSTR750UME, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: STR750-MCKIT, STR750-SK/HIT, STR750-SK/IAR, STR750-SK/KEIL, STR750-SK/RAIS, STR750-EVAL, STX-PRO/RAIS, STX-RLINK, STR79-RVDK/CPP, STR79-RVDK, STR79-RVDK/UPG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5988 - BOARD DEVELOPMENT LOVE STR750497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5751 - KIT STARTER HITEX FOR STR750497-5748 - BOARD EVALUATION FOR STR750XF497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5750

Electrical parameters
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Figure 23. Self-referred jitter (single and long term)
Figure 24. Cycle-to-cycle jitter
difference between N+1 consecutive clock rising edges and T
difference between N+1 consecutive clock rising edges.
N should be kept sufficiently large to have a long term jitter (ex: thousands).
For N=1, this becomes the single period jitter.
See
Cycle-to-cycle jitter (N period jitter)
This corresponds to the time variation between adjacent cycles over a random sample
of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1
to N.
See
Figure 23
Figure 24
CK_PLL
ACTUAL
CK_PLL
IDEAL
CK_PLL
CK_PLL
ACTUAL
IDEAL
trigger point
n
n
T
T
Tcycle 1
single period
jitter
n+1
n+1
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Tcycle 2
n+2
---
---
long term
jitter
min
Tcycle N-1
n+N
is the minimum time
n+N