Z86E3412VSC Zilog, Z86E3412VSC Datasheet - Page 32

• Manufacturer Part Number: Z86E3412VSC
• Description: IC MICROCONTROLLER 16K 28-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E3412VSC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2 bit
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 269-1039

Table 13. DC Electrical Characteristics T
PS022901-0508
No.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Symbol
TwAS
TdAS(DS)
TwDSR
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW) Write Data Valid to DS Fall (Write)
TdDS(DW)
TdA(DR)
TdAS(DS)
Parameter
AS Low Width
Address Float to DS Fall
DS (Read) Low Width
DS (Write) Low Width
DS Fail to Read Data Req’d Valid 3.5V
Read Data to DS Rise Hold Time
DS Rise to Address Active
Delay
DS Rise to AS Fall Delay
R/W Valid to AS Rise Delay
DS Rise to R/W Not Valid
Delay
DS Rise to Write Data Not Valid
Delay
Address Valid to Read Data Req’d
Valid
AS Rise to DS Fall Delay
A
= 0 °C to +70 °C, 12 MHz (Continued)
V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
CC
1
CMOS Z8
Min
55
55
0
0
200
200
110
110
0
0
45
55
30
45
45
45
45
45
55
55
45
55
65
65
®
Max
150
150
310
310
Product Specification
OTP Microcontrollers
Electrical Characteristics
Units Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3
2,3
2
2
2,3
2,3
2,3
2,3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2,3
2,3
2
2
28