Z86E4312VSG Zilog, Z86E4312VSG Datasheet - Page 60

• Manufacturer Part Number: Z86E4312VSG
• Description: IC MICROCONTROLLER 4K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4312VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 236 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3978; Z86E4312VSG

PS022901-0508
C1
C2
Ceramic Resonator or Crystal
C1, C2 = 33 pF
f = 8 MHz
* Typical value including pin parasitics
XTAL1
XTAL2
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is
used for the Power-On Reset (POR) timer function. The POR timer allows V
oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
1. Power fail to Power OK status
2. Stop Mode Recovery (if D5 of SMR=0)
3. WDT time-out
The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines
whether the POR timer is by-passed after Stop Mode Recovery (typical for an external
clock and RC/LC oscillators with fast start up times).
HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers
and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by
interrupts, either externally or internally generated. An interrupt request must be executed
(enabled) to exit HALT Mode. After the interrupt service routine, the program continues
from the instruction after the HALT. In order to enter STOP or HALT Mode, it is neces-
sary to first flush the instruction pipeline to avoid suspending execution in mid-instruc-
tion. To do this, you must execute a NOP (Opcode = FFh) immediately before the
appropriate sleep instruction, that is:
TYP *
Figure 29. Oscillator Configuration
V
SS
C1
C2
LC
C1, C2 = 22 pF
**
L = 130 μH *
f = 3 MHz
L
XTAL1
XTAL2
C1
CMOS Z8
@ 5V V
C1 = 100 pF *
R = 2K *
RC
f = 6 MHz *
R
CC
®
(TYP)
Product Specification
OTP Microcontrollers
XTAL1
XTAL2
Electrical Characteristics
CC
External Clock
and the
XTAL1
XTAL2
56