STR755FR0H6 STMicroelectronics, STR755FR0H6 Datasheet - Page 69
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STR755FR0H6
Manufacturer Part Number
STR755FR0H6
Description
MCU 32BIT 64KB FLASH 64LFBGA
Manufacturer
STMicroelectronics
Series
STR7r
Datasheet
1.STR750FV0T6.pdf
(84 pages)
Specifications of STR755FR0H6
Core Processor
ARM7
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, SPI, SSI, SSP, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFBGA
For Use With
MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5748 - BOARD EVALUATION FOR STR750XF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR755FR0H6
Manufacturer:
STMicroelectronics
Quantity:
10 000
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 41.
1. f
2. Data based on standard I
3. The maximum hold time t
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
Figure 40. Typical application with I
1. Measurement points are done at CMOS levels: 0.3xV
t
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
su(STO)
t
t
t
t
su(STA)
undefined region of the falling edge of SCL.
h(SDA)
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
PCLK
C
not possible to power off the STR7x while some another I
powered on: otherwise, the STR7x will be powered by the protection diode.
b
SDA
SCL
I
, must be at least 8 MHz to achieve max fast I
2
t
C BUS
f(SDA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
SDA and SCL characteristics
t
h(STA)
START
4.7kΩ
t
w(SCKH)
t
r(SDA)
V
2
h(SDA)
DD
C protocol requirement, not tested in production.
t
w(SCKL)
Parameter
4.7kΩ
is not applicable
V
DD
t
su(SDA)
t
r(SCK)
100Ω
100Ω
2
C bus and timing diagram
t
h(SDA)
t
f(SCK)
SDA
SCL
2
C speed (400 kHz).
DD
STRT75X
and 0.7xV
Standard mode
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
(2)
DD
I
2
C
.
Max
1000
300
400
2
C master node remains
(2)
t
su(STA)
t
su(STO)
20+0.1C
20+0.1C
Fast mode I
Electrical parameters
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
t
(4)
w(STO:STA)
STOP
(2)
REPEATED START
b
b
Max
900
300
300
400
2
START
C
(1)
(3)
(2)
Unit
69/84
pF
μs
ns
μs
μs
μs