EZ80F92AZ020SC00TR Zilog, EZ80F92AZ020SC00TR Datasheet - Page 5

• Manufacturer Part Number: EZ80F92AZ020SC00TR
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: EZ80F92AZ020SC00T

Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued)
UP004909-0910
No
7
Issue
The UART is continually
interrupting; the user
cannot clear the interrupt.
Detailed Description
The root cause of this issue has been duplicated with certain signal
conditions after which a software instruction was executed to clear the
receive FIFO. The signals involved were from bit 0 of the ISR, and the
trigger counter with RXFIFO enabled and RXINTERRUPT disabled.
Workarounds
To prevent this error condition from occurring, you can perform one of
the following two actions:
(1)Do not enable the transmit or receive FIFO if it is not required. The
(2)If you are using either the transmit or receive FIFOs, mask off the
(3)To correct this error condition when the UART Rx interrupt occurs but
//=====================workaround=====================
/*
* Check for ‘stuck’ Fifo
*/
if( (Iir == SD_IIR_RX_INT) && ((Lsr & LSR_DR) == ) )
{
UINT32 Mcr;
/*
* To clear this condition, put the Uart in loopback
* mode and send a character
*/
Mcr = BSP_RD32 ( pUART->Base|UART_REG_MCTL );
BSP_WR32( pUart->Base|UART_REG_MCTL, Mcr | MCTL_LOOP);
BSP_WR32( pUart->Base|UART_REG_THR, ‘Z’ );
/*
* Wait for the character to hit the Rx fifo
*/
Lsr = BSP_RD32( pUart->Base | UART_REG_LSR );
while( !(Lsr & LSR_DR) )
{
Lsr = BSP_RD32( pUart->Base | UART_REG_LSR );
}
(continued)
Receive FIFO was the initial problem; however, both the TX and RX
FIFOs are affected. Set bit 0 (FIFOEN) of the UART0_FCTL
(0x0C2h) or UART1_FCTL (0x0D2h) registers to a value of zero.
following two bit locations to avoid changing the default bit value of
zero. If bit 0 (FIFOEN) of the UART0_FCTL (0x0C2h) or
UART1_FCTL (0x0D2h) registers is set to 1, then mask off bit 1
(CLRRxF) and bit 2 (CLRTxF) so that any Write accesses to the
UART0_FCTL (0x0C2h) or UART1_FCTL (0x0D2h) registers will
not alter this default zero value.
there is no Rx data detected, the user can clear the condition in
software by putting the UART in loopback mode and then
transmitting a single character. The following is an example of this
workaround:
Product Update: Errata for eZ80F92 and eZ80F93 MCUs
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