STM32F103T8U6 STMicroelectronics, STM32F103T8U6 Datasheet - Page 93

MCU 32BIT ARM 64K FLASH 36VFQFPN

STM32F103T8U6

Manufacturer Part Number
STM32F103T8U6
Description
MCU 32BIT ARM 64K FLASH 36VFQFPN
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103T8U6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
26
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
36-VFQFN, 36-VFQFPN
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
CAN/I2C/SPI/USART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ST-LINK
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10-ch x 12-bit)
Controller Family/series
(ARM Cortex) STM32
No. Of I/o's
26
Ram Memory Size
20KB
Cpu Speed
72MHz
No. Of Timers
4
No. Of Pwm Channels
12
Rohs Compliant
Yes
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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STM32F103x8, STM32F103xB
Table 59.
22-May-2008
14-Mar-2008
21-Mar-2008
Date
Document revision history (continued)
Revision
5
6
7
Figure 2: Clock tree on page 12
Maximum T
page
CRC feature added (see
unit on page 9
I
Stop and Standby
ACC
note 2 removed.
P
in
t
V
page
Table 41: SPI characteristics on page 67
I
Table 47: ADC accuracy - limited test conditions
accuracy
LQFP100 package specifications updated (see
characteristics on page
Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36
footprints added (see
Section 6.2: Thermal characteristics on page 86
Section 6.2.1
Appendix A: Important notes on page 81
Small text changes.
In
– N
– cycling conditions specified for t
– t
V
CRC feature removed.
CRC feature added back. Small text changes.
modified.
I
current consumptions in Stop and Standby modes on page
I
Standby mode on page
Values added to
V) on page
Figure 32: SPI timing diagram - slave mode and CPHA = 0 on page 68
modified.
t
data retention on page
V
Figure 54: LQFP100 P
Axx option added to
page
DD
RET
VREF
DD
DD_VBAT
RET
D
NF(NRST)
25
USB
Table 28: Flash memory characteristics on page
Table 29: Flash memory endurance and data
, T
RET
Doc ID 13587 Rev 12
, Avg_Slope and T
modified in
END
at T
HSI
modified in
at T
A
36.
63.
89.
added to
added to
and T
min modified at T
A
modified in
tested over the whole temperature range
A
removed from
max = 105 °C added to
modified.
Section 2.2: Full compatibility throughout the family
Equation 1
= 105 °C modified in
unit corrected in
66.
J
J
value given in
added, t
and
and
Table 16: Typical and maximum current consumptions in
Table 43: USB DC electrical characteristics on page
Table 45: ADC characteristics on page
Table 29: Flash memory endurance and data
Table 40: SCL frequency (f
Section 6.2.2
modes.
Figure 10: Memory map on page 32
Table 24: HSI oscillator characteristics on page
Figure 10: Memory map
Table 58: Ordering information scheme on
corrected.
Figure
prog
L
D
55.
modified in
Table 21: Typical current consumption in
76).
A
47.
max vs. T
CRC (cyclic redundancy check) calculation
= 55 °C
values modified and t
Table 37: NRST pin characteristics on
Table 8: Thermal characteristics on
47,
Changes
Table 29: Flash memory endurance and
added.
added.
Figure
Table 16: Typical and maximum
RET
A
Table 49: TS
on page 88
49,
modified.
removed.
Figure 53
PCLK1
clarified.
Section 1: Introduction
prog
Section 6: Package
modified.
retention:
added.
characteristics.
modified,
= 36 MHz.,V
54.
description clarified
Revision history
and
71.
Table 48: ADC
for address).
Figure
43.
added.
retention.
DD
= 3.3
41).
93/96
53,
70.

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