Z8F0422SJ020EG Zilog, Z8F0422SJ020EG Datasheet - Page 148

• Manufacturer Part Number: Z8F0422SJ020EG
• Description: IC ENCORE MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0422SJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z8F042xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4142; Z8F0422SJ020EG

PS022517-0508
Follow the steps below for a transmit operation on a 10-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
5. Software asserts the START bit of the I
6. The I
7. The I
8. After one bit of address is shifted out by the SDA signal, the Transmit Interrupt is
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. If the I
12. The I
13. The I
14. Software responds by writing a data byte to the I
15. The I
16. If the I
I
Register.
asserted.
Data Register.
signal.
during the next high period of SCL, the I
Status register. Continue with
If the slave does not acknowledge the first address byte, the I
NCKI bit and clears the ACK bit in the I
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
Register.
bit has been sent, the Transmit Interrupt is asserted.
signal.
high period of SCL, the I
Continue with
If the slave does not acknowledge the second address byte or one of the data bytes, the
2
C Data Register. The least-significant bit must be 0 for the write operation.
2
2
2
2
2
2
2
C interrupt asserts because the I
C Controller sends the START condition to the I
C Controller loads the I
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. After the first
C Controller completes shifting the contents of the shift register on the SDA
2
2
C Slave acknowledges the first address byte by pulling the SDA signal low
C Slave sends an acknowledge by pulling the SDA signal low during the next
step
17.
2
C Controller sets the ACK bit in the I
2
2
step
C Shift register with the contents of the I
C Shift register with the contents of the I
12.
2
2
C Control Register.
C Control Register to enable Transmit interrupts.
2
C Data Register is empty.
2
C Control Register.
2
2
C Status register. Software responds to the
C Controller sets the ACK bit in the I
2
C Data Register.
Z8 Encore! XP
2
C Slave.
Product Specification
2
C Controller sets the
2
C Status register.
®
F0822 Series
2
2
C Data
C Data
I2C Controller
2
C
2
C
135