W78L801A24LL Nuvoton Technology Corporation of America, W78L801A24LL Datasheet
W78L801A24LL
Specifications of W78L801A24LL
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W78L801A24LL Summary of contents
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Table of Contents- 1. GENERAL DESCRIPTION ......................................................................................................... 2 2. FEATURES ................................................................................................................................. 2 3. PIN CONFIGURATIONS ............................................................................................................ 3 4. PIN DESCRIPTION..................................................................................................................... 5 5. BLOCK DIAGRAM ...................................................................................................................... 6 6. FUNCTIONAL DESCRIPTION ................................................................................................... 7 6.1 Interrupt System ................................................................................................................ 8 7. ELECTRICAL CHARACTERISTICS......................................................................................... 14 ...
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... Wake-up via external interrupts at Port 1 EMI reduction mode Built-in power management Code protection mechanism Packages: − DIP 40: W78L801-24 − PLCC 44: W78L801P-24 − PQFP 44: W78L801F-24 − Lead Free (RoHs)DIP 40: − Lead Free (RoHs)PLCC 44: W78L801A24PL − Lead Free (RoHs)PQFP 44: W78L801A24FL − Lead Free (RoHs)LQFP 48: W78L801A24LL W78L801A24DL - 2 - W78L801 ...
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PIN CONFIGURATIONS 40-Pin DIP 44-Pin PLCC ...
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LQFP NC 1 INT7, P1.5 2 INT8, P1.6 3 INT9, P1.7 4 RST 5 RXD, P3.0 6 P4.3 7 TXD, P3.1 8 INT0, P3.2 9 INT1, P3.3 10 T0, P3.4 11 T1, P3 W78L801 36 ...
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PIN DESCRIPTION SYMBOL EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and EA data will not be presented on the bus ...
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BLOCK DIAGRAM P1.0 Port 1 Port 1 Latch P1.7 INT2~9 Interrupt Timer 0 Timer 1 P3.0 Port 3 Port 3 Latch P3.7 Port 4 P4.0 Latch Port 4 P4.6 XTAL1 ACC Stack PSW Pointer ALU SFR ...
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FUNCTIONAL DESCRIPTION The W78L801 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, two timer/counters. The processor supports 111 different opcodes and references both a 64K program address space ...
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User’s applications should elude the ALE pulses before software configure it with I/O port P4.5. Bit: Mnemonic: P4 6.1 Interrupt System The W78L801 has twelve interrupt sources: INT0 and INT1 ; Timer 0,1; INT2 to ...
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Note interrupt disabled interrupt enabled. Interrupt Priority Register 0 Bit: IP.7: Unused. PS1: This bit defines the Serial port 1 interrupt priority sets it to higher priority level. PT2: This bit defines the ...
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Interrupt Request Flag Register Bit: Mnemonic: IRQ IQ9: External interrupt 9 request flag. IQ8: External interrupt 8 request flag. IQ7: External interrupt 7 request flag. IQ6: External interrupt 6 request flag. IQ5: External interrupt 5 request flag. IQ4: External interrupt ...
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Watchdog Timer Control Register Bit: ENW ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. ...
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Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 Clock The W78L801 is ...
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Reduce EMI Emission Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise can be turned off to reduce the EMI emission ...
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ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 DC ...
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DC Characteristics, continued PARAMETER Input Low Voltage [*3] RST Input Low Voltage [*3] XTAL1 Input High Voltage P1, P2, P3, P4 Input High Voltage RST Input High Voltage [*4] XTAL1 Output Low Voltage P1, P2, P3, P4 <0:4> Output Low ...
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DC Characteristics, continued PARAMETER Source Current P1, P2, P3, P4<0:4> Source Current P0, ALE, PSEN , P4<5:6> Notes: *1. RST pin has an internal pull-down. *2. Pins of P1 and P3 can source a transition current when they are being ...
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Program Fetch Cycle PARAMETER Address Valid to ALE Low Address Hold from ALE Low PSEN ALE Low to Low PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width PSEN Pulse Width ...
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Port Access Cycle PARAMETER Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are ...
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TIMING WAVEFORMS 8.1 Program Fetch Cycle S1 XTAL1 ALE PSEN PORT 2 T AAH PORT 0 A0-A7 Code 8.2 Data Read Cycle S4 S5 XTAL1 ALE PSEN PORT 2 A0-A7 PORT ...
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Timing Waveforms, continued 8.3 Data Write Cycle S4 S5 XTAL1 ALE PSEN PORT 2 PORT 0 A0-A7 WR 8.4 Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE A8-A15 DATA OUT T DAD T ...
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PACKAGE DIMENSIONS 9.1 40-pin DIP 9.2 44-pin PLCC θ Seating Plane ...
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PQFP See Detail F y Seating Plane 9.4 48-pin LQFP See Detail F Seating Plane 33 ...
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TYPICAL APPLICATION CIRCUIT 10.1 Keyboard 31 VCC 10U 09 VCC RESET 8.2K 14 VCC P3 W78L801 P00 38 P01 VCC PH1 R5 21 P20 ...
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REVISION HISTORY VERSION DATE A5 July 8, 2002 A6 Dec. 30, 2004 A7 April 19, 2005 A8 Aug. 25, 2005 A9 Oct. 3, 2005 A10 June 04, 2006 Winbond products are not designed, intended, authorized or warranted for use ...