ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 35

• Manufacturer Part Number: ATMEGA2560V-8AU
• Description: IC AVR MCU 256K 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Inputs: 16-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 86
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Timers: 2-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8
10.9
10.10 Rev. 2549C-09/05
2549LS–AVR–08/07
Rev. 2549E-04/06
Rev. 2549D-12/05
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Advanced Information Status changed to Preliminary.
Changed number of I/O Ports from 51 to 54.
Updatet typos in
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Updated Features in
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Updated Stabilizing Time in
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Updated Note for
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low and high period SPI clock must be larger than 2 CPU cycles.
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64M2.
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“Resources” on page
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“Features” on page
Table 12-1 on page
“Prescaling and Conversion Timing” on page
“Maximum speed vs. V
“Ordering Information” on page
Table 31-7 on page 379
“Filling the Temporary Buffer (Page Loading)” on page
“Typical Characteristics” on page
“Packaging Information” on page
“Errata” on page
“Bit Rate Generator Unit” on page
“Maximum speed vs. V
“Ordering Information” on page
“Packaging Information” on page
“Errata” on page
Figure 26-1 on page
“SPI – Serial Peripheral Interface” on page
“Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
and
“ADCSRB – ADC Control and Status Register B” on page
Table 26-6 on page
Table 12-1 on page
“TCCR0A – Timer/Counter Control Register A” on page
Table 4 on page
in“ADC – Analog to Digital Converter” on page 275
“ADC – Analog to Digital Converter” on page
ATmega640/1280/1281/2560/2561
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“Changing Channel or Reference Selection”
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CC
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“Features” on page
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Figure 26-9 on page
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Table 31-8 on page
Table 13-14 on page
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Figure 26-10
Table 26-3
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