DSPIC30F6012T-20E/PF Microchip Technology, DSPIC30F6012T-20E/PF Datasheet - Page 220
![IC DSPIC MCU/DSP 144K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC30F6012T-20E/PF
Manufacturer Part Number
DSPIC30F6012T-20E/PF
Description
IC DSPIC MCU/DSP 144K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6014-20IPF.pdf
(228 pages)
3.DSPIC30F6014-20IPF.pdf
(22 pages)
4.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6012T-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6012T20EP
dsPIC30F6011A/6012A/6013A/6014A
D
Data Accumulators and Adder/Subtractor........................... 21
Data Address Space ........................................................... 31
Data Converter Interface (DCI) Module ............................ 125
Data EEPROM Memory ...................................................... 57
DC Characteristics ............................................................ 173
DCI Module
DS70143C-page 218
Data Space Write Saturation ...................................... 23
Overflow and Saturation ............................................. 21
Round Logic ................................................................ 22
Write Back................................................................... 22
Alignment .................................................................... 34
Alignment (Figure) ...................................................... 35
Effect of Invalid Memory Accesses (Table)................. 34
MCU and DSP (MAC Class) Instructions Example..... 34
Memory Map ............................................................... 31
Memory Map for dsPIC30F6011/6013 ........................ 32
Memory Map for dsPIC30F6012/6014 ........................ 33
Near Data Space ........................................................ 35
Software Stack ............................................................ 35
Spaces ........................................................................ 31
Width ........................................................................... 34
Erasing ........................................................................ 58
Erasing, Block ............................................................. 58
Erasing, Word ............................................................. 58
Protection Against Spurious Write .............................. 61
Reading....................................................................... 57
Write Verify ................................................................. 61
Writing ......................................................................... 59
Writing, Block .............................................................. 60
Writing, Word .............................................................. 59
BOR .......................................................................... 181
Brown-out Reset ....................................................... 180
I/O Pin Input Specifications ....................................... 178
I/O Pin Output Specifications .................................... 179
Idle Current (I
Low-Voltage Detect................................................... 179
LVDL ......................................................................... 180
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 181
Bit Clock Generator................................................... 129
Buffer Alignment with Data Frames .......................... 131
Buffer Control ............................................................ 125
Buffer Data Alignment ............................................... 125
Buffer Length Control ................................................ 131
COFS Pin .................................................................. 125
CSCK Pin .................................................................. 125
CSDI Pin ................................................................... 125
CSDO Mode Bit ........................................................ 132
CSDO Pin ................................................................. 125
Data Justification Control Bit ..................................... 130
Device Frequencies for Common Codec
Digital Loopback Mode ............................................. 132
Enable ....................................................................... 127
Frame Sync Generator ............................................. 127
Frame Sync Mode Control Bits ................................. 127
I/O Pins ..................................................................... 125
Interrupts ................................................................... 132
Introduction ............................................................... 125
Master Frame Sync Operation .................................. 127
Operation .................................................................. 127
Operation During CPU Idle Mode ............................. 132
Operation During CPU Sleep Mode .......................... 132
CSCK Frequencies (Table)............................... 129
IDLE
) .................................................... 176
DD
)............................................. 175
PD
) ........................................ 177
Development Support ....................................................... 169
Device Configuration
Device Configuration Registers
Device Overview................................................................... 9
Disabling the UART .......................................................... 105
Divide Support .................................................................... 18
DSP Engine ........................................................................ 19
Dual Output Compare Match Mode .................................... 88
E
Electrical Characteristics .................................................. 173
Enabling and Setting Up UART
Enabling the UART ........................................................... 105
Equations
Errata .................................................................................... 8
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 183
External Interrupt Requests ................................................ 49
Receive Slot Enable Bits .......................................... 130
Receive Status Bits................................................... 131
Register Map ............................................................ 134
Sample Clock Edge Control Bit ................................ 130
Slave Frame Sync Operation.................................... 128
Slot Enable Bits Operation with Frame Sync............ 130
Slot Status Bits ......................................................... 132
Synchronous Data Transfers .................................... 130
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 130
Transmit Status Bits.................................................. 131
Transmit/Receive Shift Register ............................... 125
Underflow Mode Control Bit...................................... 132
Word Size Selection Bits .......................................... 127
Register Map ............................................................ 159
FBORPOR ................................................................ 157
FGS .......................................................................... 157
FOSC........................................................................ 157
FWDT ....................................................................... 157
Instructions (Table) ..................................................... 18
Multiplier ..................................................................... 21
Continuous Pulse Mode.............................................. 88
Single Pulse Mode...................................................... 88
AC............................................................................. 182
DC ............................................................................ 173
Setting Up Data, Parity and Stop Bit Selections ....... 105
ADC Conversion Clock ............................................. 137
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 129
COFSG Period.......................................................... 127
Serial Clock Rate ...................................................... 100
Time Quantum for Clock Generation ........................ 117
Type A, B and C Timer ............................................. 189
Type A Timer ............................................................ 189
Type B Timer ............................................................ 190
Type C Timer ............................................................ 190
AC-Link Mode................................................... 195
Multichannel, I
AC-Link Mode................................................... 195
Multichannel, I
2
2
S Modes................................... 193
S Modes................................... 194
© 2006 Microchip Technology Inc.