DSPIC30F6011A-30I/PF Microchip Technology, DSPIC30F6011A-30I/PF Datasheet - Page 133
![IC DSPIC MCU/DSP 132K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC30F6011A-30I/PF
Manufacturer Part Number
DSPIC30F6011A-30I/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
9.DSPIC30F6011A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6011A-30I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
52
Flash Memory Size
132KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011A-30I/PF
Manufacturer:
MICROCHIP
Quantity:
966
Company:
Part Number:
DSPIC30F6011A-30I/PF
Manufacturer:
MICROCHIP
Quantity:
316
Company:
Part Number:
DSPIC30F6011A-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
18.7
The DCI module is configured for I
a value of ‘01’ to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I
DCI module will generate frame synchronization
signals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
© 2008 Microchip Technology Inc.
I
2
S Mode Operation
dsPIC30F6011A/6012A/6013A/6014A
2
S mode by writing
2
S mode, the
18.7.1
The WS and COFSG control bits are set to produce the
period for one half of an I
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01 will produce a CPU interrupt,
once per I
18.7.2
As per the I
default, begin one CSCK cycle after a transition of the
WS signal. A MSb left justified option can be selected
using the DJST control bit in the DCICON1 SFR.
If DJST = 1, the I
justified. The MSb of the data word will be presented on
the CSDO pin during the same CSCK cycle as the
rising or falling edge of the COFS signal. The CSDO
pin is tri-stated after the data word has been sent.
2
S frame.
2
I
LENGTH SELECTION
I
S specification, a data word transfer will, by
2
2
S FRAME AND DATA WORD
S DATA JUSTIFICATION
2
S data transfers will be MSb left
2
S data frame. That is, the
DS70143D-page 133