PIC18LF6722-I/PT Microchip Technology, PIC18LF6722-I/PT Datasheet - Page 149
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6722-I/PT
Manufacturer Part Number
PIC18LF6722-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18LF6627-IPT.pdf
(16 pages)
Specifications of PIC18LF6722-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF6722-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- PIC18LF6627-IPT PDF datasheet #4
- Current page: 149 of 446
- Download datasheet (7Mb)
TABLE 11-9:
© 2008 Microchip Technology Inc.
RE0/AD8/
RD/P2D
RE1/AD9/
WR/P2C
RE2/AD10/
CS/P2B
RE3/AD11/P3C
RE4/AD12/P3B
Legend:
Note 1:
Pin Name
2:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Implemented on 80-pin devices only.
PORTE FUNCTIONS
Function
AD10
AD11
AD12
AD8
AD9
RE0
P2D
RE1
P2C
RE2
P2B
RE3
P3C
RE4
P3B
WR
RD
CS
(2)
(2)
(2)
(2)
(2)
Setting
TRIS
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
LATE<0> data output.
PORTE<0> data input.
External memory interface, address/data bit 8 output. Takes priority
over ECCP and port data.
External memory interface, data bit 8 input.
Parallel Slave Port read enable control input.
ECCP2 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<1> data output.
PORTE<1> data input.
External memory interface, address/data bit 9 output. Takes priority
over ECCP and port data.
External memory interface, data bit 9 input.
Parallel Slave Port write enable control input.
ECCP2 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<2> data output.
PORTE<2> data input.
External memory interface, address/data bit 10 output. Takes priority
over ECCP and port data.
External memory interface, data bit 10 input.
Parallel Slave Port chip select control input.
ECCP2 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<3> data output.
PORTE<3> data input.
External memory interface, address/data bit 11 output. Takes priority
over ECCP and port data.
External memory interface, data bit 11 input.
ECCP3 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<4> data output.
PORTE<4> data input.
External memory interface, address/data bit 12 output. Takes priority
over ECCP and port data.
External memory interface, data bit 12 input.
ECCP3 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
PIC18F8722 FAMILY
Description
DS39646C-page 147
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