AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 332
![IC AVR MCU 128K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90USB1287-AU
Manufacturer Part Number
AT90USB1287-AU
Description
IC AVR MCU 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Specifications of AT90USB1287-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR USB
No. Of I/o's
48
Eeprom Memory Size
4KB
Ram Memory Size
8KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB1287-16AU
AT90USB1287-16AU
AT90USB1287-16AU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB1287-AU
Manufacturer:
ATMEL
Quantity:
1 459
Part Number:
AT90USB1287-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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26. JTAG Interface and On-chip Debug System
26.0.1
26.1
26.2
332
Overview
Test Access Port – TAP
AT90USB64/128
Features
•
•
•
•
•
•
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections
ming via the JTAG Interface” on page 385
338, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within ATMEL and to selected third party vendors only.
Figure 26-1
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG
instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
• Testing PCBs by using the JTAG Boundary-scan capability
• Programming the non-volatile memories, Fuses and Lock bits
• On-chip debugging
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
• TCK: Test Clock. JTAG operation is synchronous to TCK.
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
machine.
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
shows a block diagram of the JTAG interface and the On-chip Debug system. The
and
®
“IEEE 1149.1 (JTAG) Boundary-scan” on page
7593K–AVR–11/09
“Program-
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