PIC17C756A-33E/L Microchip Technology, PIC17C756A-33E/L Datasheet - Page 34
![IC MCU CMOS 33MHZ 16K EPRM68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17C756A-33E/L
Manufacturer Part Number
PIC17C756A-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
6.1
The Interrupt Status/Control register (INTSTA) contains
the flag and enable bits for non-peripheral interrupts.
The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR registers (Figure 6-4 and
Figure 6-5).
REGISTER 6-1: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
DS30289B-page 34
Note:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Interrupt Status Register (INTSTA)
All interrupt flag bits get set by their speci-
fied condition, even if the corresponding
interrupt enable bit is clear (interrupt dis-
abled), or the GLINTD bit is set (all inter-
rupts disabled).
Legend:
R = Readable bit
- n = Value at POR Reset
bit 7
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
The interrupt logic forces program execution to address (20h) when a peripheral interrupt is
pending.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit acts as a global enable bit for the peripheral interrupts that have their corresponding
enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
PEIF
R-0
T0CKIF
R/W-0
R/W-0
T0IF
W = Writable bit
’1’ = Bit is set
R/W-0
INTF
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is cleared,
the device will vector to the RESET address (0x00).
Prior to disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
PEIE
T0CKIE
R/W-0
2000 Microchip Technology Inc.
x = Bit is unknown
R/W-0
T0IE
R/W-0
INTE
bit 0
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