AT89C51CC03UA-RDTUM Atmel, AT89C51CC03UA-RDTUM Datasheet - Page 62
![IC 8051 MCU FLASH 64K 64-VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C51CC03UA-RDTUM
Manufacturer Part Number
AT89C51CC03UA-RDTUM
Description
IC 8051 MCU FLASH 64K 64-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-RDTUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 31. Serial I/O Port Block Diagram
Figure 32. Framing Error Block Diagram
62
Framing Error Detection
Serial I/O Port
AT89C51CC03
TXD
RXD
The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
The software may examine the FE bit after each reception to check for data errors.
Once set, only software or a reset clears the FE bit. Subsequently received frames with
SM0/FE
SMOD
Framing error detection
Automatic address recognition
Transmitter
SMOD0
SBUF
SM1
SM2
-
Mode 0 Transmit
IB Bus
Write SBUF
SCON reg
RI
REN
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
POF
To UART framing error control
TI
TB8
GF1
RB8
GF0
Shift register
Receive
Receiver
SBUF
PD
TI
IDL
RI
Load SBUF
Read SBUF
Serial Port
Interrupt
Request
4182O–CAN–09/08
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