DSPIC30F6010A-20E/PF Microchip Technology, DSPIC30F6010A-20E/PF Datasheet - Page 22

• Manufacturer Part Number: DSPIC30F6010A-20E/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010A-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 4.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F Family Reference Manual
35.5
35.5.1
35.5.1.1
35.5.1.2
35.5.2
DS70272B-page 35-22
Sleep Mode
Master Mode Operation
Slave Mode Operation
Idle Mode
Operation in Power-Saving Modes
The dsPIC30F SMPS and Digital Power Conversion device family has three power modes: the
normal operational (Full-Power) mode and the two power-saving modes invoked by the PWRSAV
instruction. Depending on the SPI mode selected, entering a power-saving mode may also affect
the operation of the SPI1 module.
When the device enters Sleep mode, the system clock is disabled. The consequences of
entering Sleep mode depend on which mode (Master or Slave) the SPI1 module is configured
for at the time that Sleep mode is invoked.
The consequences of entering Sleep mode when the SPI1 module is configured for Master
operation are as follows:
• The Baud Rate Generator in the SPI1 module stops and is reset.
• The transmitter and receiver will stop in Sleep mode. The transmitter or receiver does not
• If the SPI1 module enters Sleep mode in the middle of a transmission or reception, the
Since the clock pulses at SCK1 are externally provided for Slave mode, the module will continue
to function in Sleep mode. It will complete any transactions during the transition into Sleep mode.
On completion of a transaction, the SPIRBF flag is set. Consequently, the SPI1IF bit will be set.
If SPI1 interrupts are enabled (SPI1IE = 1), the device will wake from Sleep mode. If the SPI1
interrupt priority level is greater than the present CPU priority level, code execution will resume
at the SPI1 interrupt vector location. Otherwise, code execution will continue with the instruction
following the PWRSAV instruction that previously invoked Sleep mode. The module is not Reset
on entering Sleep mode if it is operating as a slave device.
The register contents are not affected when the SPI1 module is going into or coming out of Sleep
mode.
When the device enters Idle mode, the system clock sources remain functional. The SPISIDL bit
(SPI1STAT<13>) selects whether the module will stop or continue functioning on Idle mode.
If SPISIDL = 1, the SPI1 module will stop communication on entering Idle mode. It will operate
in the same manner as it does in Sleep mode. If SPISIDL = 0 (default selection), the module will
continue operation in Idle mode.
continue with a partially completed transmission at wake-up.
transmission or reception is aborted. Since there is no automatic way to prevent an entry
into Sleep mode if a transmission or reception is pending, the user application must
synchronize entry into Sleep mode with SPI1 module operation to avoid aborted
transmissions.
© 2008 Microchip Technology Inc.