ATMEGA649-16AU Atmel, ATMEGA649-16AU Datasheet - Page 58

IC AVR MCU FLASH 64K 64TQFP

ATMEGA649-16AU

Manufacturer Part Number
ATMEGA649-16AU
Description
IC AVR MCU FLASH 64K 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA649-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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12.2.6
12.2.7
58
ATmega329/3290/649/6490
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit
(0x6C)
Read/Write
Initial Value
Bit
(0x6B)
Read/Write
Initial Value
R/W
PCINT15
7
PCINT7
0
R/W
7
0
6
PCINT6
R/W
0
PCINT14
R/W
6
0
5
PCINT5
R/W
0
PCINT13
R/W
5
0
4
PCINT4
R/W
0
PCINT12
R/W
4
0
PCINT11
3
PCINT3
R/W
0
R/W
3
0
PCINT10
2
PCINT2
R/W
0
R/W
2
0
1
PCINT1
R/W
0
PCINT9
R/W
1
0
0
PCINT0
R/W
0
PCINT8
R/W
0
0
PCMSK0
PCMSK1
2552K–AVR–04/11

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