PIC32MX675F512L-80I/PT Microchip Technology, PIC32MX675F512L-80I/PT Datasheet - Page 56

IC MCU 32BIT 512KB FLASH 100TQFP

PIC32MX675F512L-80I/PT

Manufacturer Part Number
PIC32MX675F512L-80I/PT
Description
IC MCU 32BIT 512KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX675F512L-80I/PT

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX675F512L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX675F512L-80I/PT
0
PIC32MX
TABLE 19-3:
TABLE 19-4:
DS61145G-page 56
bit 7
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
ETAP_ADDRESS
ETAP_DATA
ETAP_CONTROL
ETAP_EJTAGBOOT
ETAP_FASTDATA
CPS
Command
CPS: Code-Protect State bit
0 = Device is code-protected
1 = Device is NOT code-protected
Unimplemented: Read as ‘0’
CFGRDY: Code-Protect State bit
0 = Configuration has not been read
1 = Configuration has been read and CP is valid
FCBUSY: Flash Controller Busy bit
0 = Flash Controller is Not Busy (either erase has not started or it has finished)
1 = Flash Controller is Busy (Erase is in progress)
FAEN: Flash Access Enable bit
This bit reflects the state of CFGCON.FAEN.
0 = Flash access is disabled (i.e., processor accesses are blocked)
1 = Flash access is enabled
DEVRST: Device Reset State bit
0 = Device Reset is NOT active
1 = Device Reset is active
MCHP STATUS VALUE
EJTAG TAP INSTRUCTIONS
0
Value
5’h0A
5’h0C
5’h0E
0
5’h08
5’h09
Select Address register.
Select Data register.
Select EJTAG Control register.
Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as Reset value.
Selects the Data and Fastdata registers.
0
CFGRDY
FCBUSY
Description
© 2010 Microchip Technology Inc.
FAEN
DEVRST
bit 0

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