AT89C51AC3-SLSUM Atmel, AT89C51AC3-SLSUM Datasheet - Page 116

IC 8051 MCU FLASH 64K 44PLCC

AT89C51AC3-SLSUM

Manufacturer Part Number
AT89C51AC3-SLSUM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51AC3-SLSUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
3
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44PLCC
Device Core
8051
Family Name
89C
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51AC3-SLSUM
Manufacturer:
Atmel
Quantity:
10 000
116
AT89C51AC3
Table 66. IEN1 Register
IEN1 (S:E8h)
Interrupt Enable Register
Reset Value = xxxx 0x0xb
bit addressable
Number
Bit
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
EADC
ESPI
Bit
6
-
-
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPI Interrupt Enable bit
Clear to disable the SPI interrupt.
Set to enable the SPI interrupt.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ADC Interrupt Enable bit
Clear to disable the ADC interrupt.
Set to enable the ADC interrupt.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
4
-
ESPI
3
2
-
4383D–8051–02/08
EADC
1
0
-

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