AT32UC3A3256-ALUR Atmel, AT32UC3A3256-ALUR Datasheet - Page 37

• Manufacturer Part Number: AT32UC3A3256-ALUR
• Description: IC MCU 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A3256-ALUR

• Package / Case: 144-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 66MHz
• Number Of I /o: 110
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4.11
8.4.12
8.4.13
32072AS–AVR32–03/09
Peripheral DMA Controller
DMA Controller
General-Purpose Input/Output Controller
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Serial Peripheral Interface
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Energy-saving capabilities
Error detection
SDRAM power-up initialization by software
CAS latency of one, two, and three supported
Auto Precharge command not used
8 channels
Generates transfers to/from peripherals such as USART, SSC and SPI
Two address pointers/counters per channel allowing double buffering
Performance monitors to measure average and maximum transfer latency
2 HSB Master Interfaces
4 Channels
Software and Hardware Handshaking Interfaces
Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
Single-block DMA Transfer
Multi-block DMA Transfer
DMA Controller is Always the Flow Controller
Additional Features
Each I/O line of the GPIO features:
Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line
A glitch filter providing rejection of pulses shorter than one clock cycle
Input visibility and output control
Multiplexing of up to four peripheral functions per I/O line
Programmable internal pull-up resistor
Compatible with an embedded 32-bit microcontroller
Supports communication with serial external devices
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
– Refresh error interrupt
– 9 Hardware Handshaking Interfaces
– Linked Lists
– Auto-Reloading
– Contiguous Blocks
– Scatter and Gather Operations
– Channel Locking
– Bus Locking
– FIFO Mode
– Pseudo Fly-by Operation
– Four chip selects with external decoder support allow communication with up to 15
peripherals
AT32UC3A3
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