ATSAM3S2BA-AU Atmel, ATSAM3S2BA-AU Datasheet - Page 28

• Manufacturer Part Number: ATSAM3S2BA-AU
• Description: IC MCU 32BIT 128KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S2BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 32KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5
7.6
28
Master to Slave Access
Peripheral DMA Controller
SAM3S Summary
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired and shown as “-” in the following table.
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
Instance Name
Slaves
0
1
2
3
4
USART1
USART0
UART1
UART0
HSMCI
UART1
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
PWM
TWI1
TWI0
PIOA
TWI1
TWI0
DAC
SSC
SPI
SAM3S Master to Slave Access
Peripheral DMA Controller
External Bus Interface
Channel T/R
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
100 & 64 Pins
Masters
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Cortex-M3 I/D
Bus
X
X
0
-
-
-
48 Pins
N/A
N/A
N/A
N/A
x
x
x
x
x
x
x
x
x
x
x
Cortex-M3 S
Bus
X
X
X
1
-
-
6500CS–ATARM–24-Jan-11
PDC
X
X
X
X
2
-
CRCCU
3
X
X
X
X
-