PIC17C44-16/PQ Microchip Technology, PIC17C44-16/PQ Datasheet - Page 126

• Manufacturer Part Number: PIC17C44-16/PQ
• Description: IC MCU OTP 8KX16 PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C44-16/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• For Use With: AC164316 - MODULE SKT MPLAB PM3 44MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PIC17C4X
MOVFP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS30412C-page 126
Before Instruction
After Instruction
Decode
REG1
REG2
REG1
REG2
Q1
register 'f'
Move f to p
[ label ]
0
0
(f)
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 word data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Either ’p' or 'f' can be WREG (a useful
special situation).
MOVFP is particularly useful for transfer-
ring a data memory location to a periph-
eral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
1
1
MOVFP
None
Read
011p
Q2
=
=
=
=
f
p
(p)
255
31
0x33,
0x11
0x33,
0x33
MOVFP f,p
REG1, REG2
pppp
Execute
Q3
ffff
register 'p'
Write
Q4
ffff
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Note:
Before Instruction
After Instruction
Decode
BSR register
BSR register
Q1
For the PIC17C42, only the low four bits of
the BSR register are physically imple-
mented. The upper nibble is read as '0'.
literal 'u:k'
Move Literal to low nibble in BSR
[ label ]
0
k
None
The four bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
1
1
MOVLB
Read
1011
Q2
=
=
k
(BSR<3:0>)
1996 Microchip Technology Inc.
15
0x22
0x25
MOVLB k
0x5
1000
Execute
Q3
uuuu
Write literal
BSR<3:0>
'k' to
Q4
kkkk