ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 22
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ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev. 2467M-11/04
Rev. 2467L-05/04
Rev. 2467K-03/04
Rev. 2467J-12/03
Rev. 2467I-09/03
22
ATmega128
7. Updated
8. Updated Features in
9. Added note in
10. Updated
1. Removed “analog ground”, replaced by “ground”.
2. Updated
3. Added note to
4. Updated
1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ICx
2. Updated
3. Updated
4. Updated
5. Updated
6. Updated
7. Updated
8. Updated
1. Updated
1. Updated
1. Updated note in
2. Updated
3. Updated values for V
4. Updated
5. Updated description for the JTD bit on
6. Added a note regarding JTAGEN fuse to
Table 132 on page
with ICPx.
page
Table 134 on page
242,
“Serial Peripheral Interface – SPI” on page
“Errata” on page
“Ordering Information” on page
“External Memory Interface” on page
“Device Identification Register” on page
“Electrical Characteristics” on page
“ADC Characteristics” on page
“Typical Characteristics” on page
“Ordering Information” on page
“Errata” on page
“Calibrated Internal RC Oscillator” on page
“JTAG Interface and On-chip Debug System” on page
“Test Access Port – TAP” on page 246
Table 8 on page
Table 11 on page
Table 126 on page
“Input Channel and Gain Selections” on page
“Port C (PC7..PC0)” on page
“XTAL Divide Control Register – XDIV” on page
321. Updated
323.
“Analog to Digital Converter” on page 230
BOT
(BODLEVEL = 1) in
38,
18.
18.
40,
299,
Table 19 on page
Table 114 on page
Figure 114 on page
Table 128 on page
page
325.
Table 118 on page
15.
15.
333.
5.
Table 19 on page
255.
318.
25.
50,
regarding JTAGEN.
253.
Table 22 on page
285,
162.
238.
41.
303,
Table 128 on page
Table 132 on page
288.
243.
50.
48.
36.
56,
2467VS–AVR–02/11
Table 96 on
303, and
321, and