PIC24FJ256DA110-I/BG Microchip Technology, PIC24FJ256DA110-I/BG Datasheet - Page 4
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PIC24FJ256DA110-I/BG
Manufacturer Part Number
PIC24FJ256DA110-I/BG
Description
MCU PIC 16BIT FLASH 256K 121BGA
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Specifications of PIC24FJ256DA110-I/BG
Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
121-TFBGA
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
84
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
UART, SPI, USB, I2C, RS-485, RS-232
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
23
Number Of Timers
5
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256DA110-I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJ256DA210 FAMILY
6. Module: Output Compare (Cascaded
DS80505C-page 4
When 32-bit Cascaded mode is enabled
(OCxCON2<8>
unavailable:
• Single-Shot operations when OCM
• Synchronous modes when the SYNCSEL bits
Work around
None.
Affected Silicon Revisions
A3
(OCxCON1<2:0> = 110 or 111 and OCTRIG
(OCxCON2<7>) = 1 and TRIGMODE
(OCxCON1<3>) = 1.
(OCxCON2<4:0>) ! = 00000 and OCTRIG
(OCxCON2<7>) = 0.
X
Mode)
=
1),
these
modes
are
7. Module: USB
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the host may persistently drive the bus to an
SE0 state (both D+/D- as 0) which would be
interpreted as a bus Reset condition by the hub;
or the host may persistently drive the bus to a J
state, which would make the hub detach
condition undetectable by the host.
Work around
Connect low-speed devices directly to the host
USB port and not through a USB hub.
Affected Silicon Revisions
A3
X
2011 Microchip Technology Inc.