ATMEGA1280V-8AUR Atmel, ATMEGA1280V-8AUR Datasheet - Page 238

MCU AVR 128K FLASH 8MHZ 100TQFP

ATMEGA1280V-8AUR

Manufacturer Part Number
ATMEGA1280V-8AUR
Description
MCU AVR 128K FLASH 8MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1280V-8AUR

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA1280V-8AUR
Manufacturer:
Atmel
Quantity:
10 000
22.6.2
22.6.3
2549M–AVR–09/10
UCSRnA – USART MSPIM Control and Status Register n A
UCSRnB – USART MSPIM Control and Status Register n B
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag
can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXCn
R/W
7
0
RXCIEn
R/W
7
0
TXCn
R/W
6
0
TXCIEn
R/W
6
0
UDREn
R/W
ATmega640/1280/1281/2560/2561
5
0
UDRIE
R/W
5
0
R
4
0
-
RXENn
R/W
4
0
R
3
0
-
TXENn
R/W
3
0
R
2
1
-
R
2
1
-
R
1
1
-
R
1
1
-
R
0
0
-
R
0
0
-
UCSRnB
UCSRnA
238

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