PIC18F8722-E/PT Microchip Technology, PIC18F8722-E/PT Datasheet - Page 270

• Manufacturer Part Number: PIC18F8722-E/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8722-E/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3936Byte
• Cpu Speed: 40MHz
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
20.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CKx pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any low-power
mode.
20.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 20-9:
DS39646B-page 268
INTCON
PIR1
PIE1
IPR1
TRISC
TRISG
RCSTAx
TXREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSRx register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of
TSRx, the TXREGx register will transfer the
second word to the TSRx and flag bit, TXxIF, will
now be set.
If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSARTx Transmit Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
TRISC7
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
TRISC6
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
—
TRISC5
RC1IF
RC1IE
RC1IP
SREN
TXEN
Bit 5
—
—
Preliminary
TRISC4
TRISG4
INT0IE
TX1IF
TX1IE
TX1IP
CREN
SYNC
SCKP
Bit 4
TRISG3
SSP1IF
SSP1IE
SSP1IP
TRISC3
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXxIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IE
CCP1IP
TRISG2
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
TRISG1
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
 2004 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
TRISC0
TRISG0
ABDEN
RX9D
TX9D
RBIF
Bit 0
on page
Values
Reset
57
60
60
60
60
60
59
59
59
61
61
59