PIC18F2585-I/SO Microchip Technology, PIC18F2585-I/SO Datasheet - Page 141

• Manufacturer Part Number: PIC18F2585-I/SO
• Description: IC MCU FLASH 24KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2585-I/SO

• Core Size: 8-Bit
• Program Memory Size: 48KB (24K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.25KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4680 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Details

TABLE 10-7:
© 2007 Microchip Technology Inc.
RD0/PSP0/
C1IN+
RD1/PSP1/
C1IN-
RD2/PSP2/
C2IN+
RD3/PSP3/
C2IN-
RD4/PSP4/
ECCP1/P1A
RD5/PSP5/
P1B
RD6/PSP6/
P1C
RD7/PSP7/
P1D
Legend:
Pin Name
PWR = Power Supply; OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input;
TTL = TTL Buffer Input
RD0
PSP0
C1IN+
RD1
PSP1
C1IN-
RD2
PSP2
C2IN+
RD3
PSP3
C2IN-
RD4
PSP4
ECCP1
P1A
RD5
PSP5
P1B
RD6
PSP6
P1C
RD7
PSP7
P1D
Function
PORTD I/O SUMMARY
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRIS
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
0
1
0
0
1
X
x
0
0
1
x
x
0
0
1
x
x
0
Buffer
ANA
ANA
ANA
ANA
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
PIC18F2585/2680/4585/4680
LATD<0> data output.
PORTD<0> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
Comparator 1 positive input B. Default on POR. This analog input overrides the digital
input (read as clear – low level).
LATD<1> data output.
PORTD<1> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
Comparator 1 negative input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
LATD<2> data output.
PORTD<2> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
Comparator 2 positive input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
LATD<3> data output.
PORTD<3> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
Comparator 2 negative input. Default input on POR. This analog input overrides the
digital input (read as clear – low level).
LATD<4> data output.
PORTD<4> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
ECCP1 compare output.
ECCP1 capture input.
ECCP1 Enhanced PWM output, channel A.
LATD<5> data output.
PORTD<5> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
ECCP1 Enhanced PWM output, channel B.
LATD<6> data output.
PORTD<6> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
ECCP1 Enhanced PWM output, channel C.
LATD<7> data output.
PORTD<7> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
ECCP1 Enhanced PWM output, channel D.
Preliminary
Description
DS39625C-page 139